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| CD4071BC * CD4081BC Quad 2-Input OR Buffered B Series Gate * Quad 2-Input AND Buffered B Series Gate October 1987 Revised April 2002 CD4071BC * CD4081BC Quad 2-Input OR Buffered B Series Gate * Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS. Features s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 5V-10V-15V parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 A at 15V over full temperature range Ordering Code: Order Number CD4071BCM CD4071BCN CD4081BCM CD4081BCN Package Number M14A N14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices are also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagrams CD4071B CD4081B Top View Top View (c) 2002 Fairchild Semiconductor Corporation DS005977 www.fairchildsemi.com CD4071BC * CD4081BC Schematic Diagrams CD4071B 1 /4 of device shown J=A+B Logical "1" = HIGH Logical "0" = LOW *All inputs protected by standard CMOS protection circuit. CD4081B 1 /4 of device shown J=A*B Logical "1" = HIGH Logical "0" = LOW All inputs protected by standard CMOS protection circuit. www.fairchildsemi.com 2 CD4071BC * CD4081BC Absolute Maximum Ratings(Note 1) (Note 2) Voltage at Any Pin Power Dissipation (PD) Dual-In-Line Small Outline VDD Range Storage Temperature (TS) Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 2) 700 mW 500 mW Recommended Operating Conditions Operating Range (VDD) Operating Temperature Range (TA) CD4071BC, CD4081BC 3 VDC to 15 VDC -0.5V to VDD +0.5V -55C to +125C -0.5 VDC to +18 VDC -65C to +150C Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: All voltages measured with respect to VSS unless otherwise specified. DC Electrical Characteristics CD4071BC/CD4081BC Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 3) IOH HIGH Level Output Current (Note 3) IIN Input Current VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Conditions -55C Min Max 0.25 0.5 1.0 0.05 Min +25C Typ 0.004 0.005 0.006 0 0 0 4.95 9.95 14.95 5 10 15 2 4 6 3.5 7.0 11.0 0.51 1.3 3.4 -0.51 -1.3 -3.4 3 6 9 0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5 -0.1 0.1 1.5 3.0 4.0 Max 0.25 0.5 1.0 0.05 0.05 0.05 +125C Min Max 7.5 15 30 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 -0.36 -0.9 -2.4 -1.0 1.0 Units A |IO| < 1 A 4.95 |IO| < 1 A 9.95 14.95 0.05 0.05 V V VDD = 5V, VO = 0.5V VDD = 10V, VO = 1.0V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.5V VDD = 10V, VO = 9.0V VDD = 15V, VO = 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V 3.5 7.0 11.0 0.64 1.6 4.2 -0.64 -1.6 -4.2 1.5 3.0 4.0 V V mA mA -0.1 0.1 A Note 3: IOH and IOL are tested one output at a time. AC Electrical Characteristics Symbol tPHL Parameter Propagation Delay Time, HIGH-to-LOW Level tPLH Propagation Delay Time, LOW-to-HIGH Level tTHL, tTLH Transition Time (Note 4) Conditions Typ 100 40 30 90 40 30 90 50 40 5 18 Max 250 100 70 250 100 70 200 100 80 7.5 pF pF ns ns ns Units CD4071BC TA = 25C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 k, Typical temperature coefficient is 0.3%/C VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V CIN CPD Average Input Capacitance Power Dissipation Capacity Any Input Any Gate Note 4: AC Parameters are guaranteed by DC correlated testing. 3 www.fairchildsemi.com CD4071BC * CD4081BC AC Electrical Characteristics Symbol tPHL Parameter Propagation Delay Time, HIGH-to-LOW Level tPLH Propagation Delay Time, LOW-to-HIGH Level tTHL, tTLH Transition Time (Note 5) Conditions Typ 100 40 30 120 50 35 90 50 40 5 18 Max 250 100 70 250 100 70 200 100 80 7.5 pF pF ns ns ns Units CD4081BC TA = 25C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 k, Typical temperature coefficient is 0.3%/C VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V CIN CPD Average Input Capacitance Power Dissipation Capacity Any Input Any Gate Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics www.fairchildsemi.com 4 CD4071BC * CD4081BC Typical Performance Characteristics (Continued) 5 www.fairchildsemi.com CD4071BC * CD4081BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 6 CD4071BC * CD4081BC Quad 2-Input OR Buffered B Series Gate * Quad 2-Input AND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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